The present invention relates to a semiconductor memory device; more particularly, to a semiconductor memory device for stably performing a write operation with reduced current consumption.
In a conventional semiconductor memory device, a global input/output (GIO) line is used at both of the write and read operations. A data input/output path in the write and read operations is briefly described below.
FIG. 1 is a schematic circuit diagram illustrating a data input/output path in a conventional semiconductor memory device. The semiconductor memory device includes a GIO line GIO, a termination resistor unit 10 and a storage unit 20.
The termination resistor unit 10 controls pull-up and pull-down resistance of the GIO line GIO when a read period signal RDS is activated. The storage unit 20 stores data loaded on the GIO line GIO when the read period signal RDS is inactivated.
FIG. 2 is a signal timing diagram illustrating an operation of the conventional semiconductor memory device in FIG. 1.
A read period signal RDS is activated in response to an internal read signal. The termination resistor unit 10 makes pull-up and pull-down resistance of the GIO line GIO to be identical in response to the read period signal RDS. Accordingly, a voltage on the GIO line GIO maintains a half of a supply voltage level ½ VDD. Data output from a memory cell unit is transmitted to the GIO line GIO, in order to be outputted to an external device.
After delay time corresponding to a burst length passes from activation timing of the internal read signal, at point a, the read period signal RDS is inactivated. The termination resistor unit 10 turns off and the active storage unit 20 stores the data transmitted to the GIO line GIO.
If a write operation is performed after the above read operation, an external data is inputted into the GIO line GIO in response to an internal write signal. FIG. 2 illustrates a voltage level change on the GIO line GIO in case that the write operation for a data having a high logic level is performed after the read operation for a data having a low logic level. The voltage level transitions from a ground voltage level VSS corresponding to the low logic level to a supply voltage level VDD corresponding to the high logic level.
In this way, a conventional semiconductor memory device turns off a termination resistor unit of a GIO line during the write operation. When the level of data input during the write operation is different from the level of data on the GIO line GIO, data transition from the ground voltage level VSS to the supply voltage level VDD is required. Accordingly, time for data to be inputted into the GIO line GIO increases and set-up/holding time margin needful for the next process becomes in short supply. During the next process, malfunctions can be caused by abnormal data.